bliss: BLIF to SPICE Synthesis Documentation

Introduction

bliss is a software for synthesizing BLIF files to SPICE netlists. Originally developed by Eli Mallari for his MS thesis, bliss can accept BLIF files and convert them to equivalent SPICE netlists using CMOS libraries.

As of this version, bliss supports BLIF output files of Odin II, a front-end for synthesizing Verilog to BLIF. Support for the entire BLIF specification will come soon as bliss is continually developed!

Features

• Support for output BLIF files of Odin II.
• Support for synthesizing .names and .latch BLIF declarations.
• Comes with default CMOS libraries for basic gates like AND, OR, inverter, etc.
• CMOS libraries can be extended to add support for any logic block.

Download

You can download the latest source files and CMOS libraries from SourceForge: http://sourceforge.net/projects/blissvlsi

QuickStart Guide

Requirements, installation, and examples for running Bliss can be found in the Bliss QuickStart Guide: http://blissvlsi.sourceforge.net/BlissQuickStartGuide.pdf

License

By downloading bliss you accept that bliss is provided "AS IS", free of charge, without warranty.

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Detailed License

Contact

bliss is developed and maintained by me, Noriel "Eli" Mallari. You can contact me through e-mail: noriel.mallari@gmail.com for questions and support, or if you want to contribute to the development of bliss.

Credits

Credits go to the following who greatly helped in the development of bliss:

• Dr. Peter A. Jamieson, for developing Odin II. http://www.users.muohio.edu/jamiespa/odin_II.html
• Dimitri van Heesch, for developing Doxygen. Man, your software rocks! http://www.stack.nl/~dimitri/doxygen/index.html
• Roderick Yap, for his valuable inputs and for being a very supportive thesis adviser.
• Ann Dulay, Cesar Llorente, and Edwin Sybingco, for their valuable inputs as panelists of my MS thesis.
• Patty, for the love and support.
• and others who have made development of bliss possible!

Changelog

Feb. 17, 2011

• Added '-?' support (help) in command-line.
• Modified mechanics for handling SIGNAL. Signals are now defined as short circuits in the final output circuit.
• Added feature to BlissBLIFCleaner. Cleaner now removes 'top' prefix added by Odin II so developer can make use of true input/output names from Verilog.